
2001 Microchip Technology Inc.
Advance Information
DS39541A-page 283
PIC18C601/801
FIGURE 22-13:
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
TABLE 22-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71
72
73
74
75, 76
78
79
80
79
78
MSb
LSb
Bit6 - - - - - -1
MSb In
LSb In
Bit6 - - - -1
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
70
TssL2scH,
TssL2scL
SS
↓ to SCK↓ or SCK↑ input
TCY
—
ns
71
TscH
SCK input high time
(Slave mode)
Continuous
1.25TCY + 30
—
ns
71A
Single Byte
40
—
ns
(Note 1)
72
TscL
SCK input low time
(Slave mode)
Continuous
1.25TCY + 30
—
ns
72A
Single Byte
40
—
ns
(Note 1)
73
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge
100
—
ns
73A
TB2B
Last clock edge of Byte1 to the 1st clock edge of
Byte2
1.5TCY + 40
—
ns
(Note 2)
74
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
100
—
ns
75
TdoR
SDO data output rise time
PIC18C601/801
—
25
ns
PIC18LC601/801
—
45
ns
76
TdoF
SDO data output fall time
—
25
ns
78
TscR
SCK output rise time
(Master mode)
PIC18C601/801
—
25
ns
PIC18LC601/801
—
45
ns
79
TscF
SCK output fall time (Master mode)
—
25
ns
80
TscH2doV,
TscL2doV
SDO data output valid after
SCK edge
PIC18C601/801
—
50
ns
PIC18LC601/801
—
100
ns
Note 1: Requires the use of parameter # 73A.
2: Only if parameter #s 71A and 72A are used.